Private RepositoryInvite Only
Contribute to SynthesisDeck
SynthesisDeck is developed in a private repository. To maintain code quality and security, contributor access is granted on a case-by-case basis.
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How It Works
Request access in three steps
01
Send Request
Click the button below to send an access request via email. Include your GitHub username and area of interest.
02
Review
The maintainer reviews your request and background. Most responses are sent within 48 hours.
03
Collaborate
Once approved, you'll receive a GitHub invitation. Clone the repo and start contributing.
Expectations
What we look for in contributors
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FPGA Toolchain Knowledge
Familiarity with Yosys, GHDL, nextpnr, or similar open-source FPGA tools.
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Docker Experience
Comfortable working with containerized build environments and multi-stage images.
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VS Code Extension Dev
Experience with the VS Code extension API, TypeScript, and webview panels.
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Testing & Simulation
Ability to write VHDL/Verilog testbenches and validate synthesis pipelines.
Open Areas
Where you can make an impact
01New FPGA family support (Xilinx, Altera, etc.)
02Build pipeline optimizations
03Simulation & waveform viewer integration
04UI/UX improvements for the Build Panel
05Documentation & tutorials
06Bug fixes & issue triage